FIG. 8 shows an example of an overall configuration of a programmable controller having a slave station 3A, to which a programmable controller controlling process of the background art is applied. A master station 1 is connected via a link cable 2 to slave station 3A. A central data processing module 4 provided in the master station 1 utilizes a program memory 5 for storing sequence programs. An internal device memory 6 is also provided in the central data processing module 4, and includes a link register 6a for holding information identical to that transmitted on the link cable 2, a register for storing PROCESSING EXECUTING flag 6b for indicating that data transfer to and from a slave station, e.g. 3A, is being conducted, a register for storing a PROCESSING COMPLETE flag 6c that is set when the data transfer to and from the slave station 3A, is complete and is automatically reset after a sequence program has been run twice, and registers for storing flags 6d and 6e that are required to execute a data link instruction. The processing module 4 further includes an operation processor 7 for running the sequence program sequentially and a system program memory 9 for storing an operating system and other programs for operating the central data processing module 4. A link module 8 is provided in the master station 1 between the link cable 2 and the central data processing module 4 for converting information transmitted by the link cable 2 into information acceptable by the central data processing module 4 as well as converting information in the central data processing module 4 into information transmittable by the link cable 2. An I/O module 10 is for controlling a unit to be controlled (not illustrated) that is connected to the master station 1.
In the slave station is at least one processing module 11 for transferring data to and from the central data processing module 4 in the master station 1. A link module 12 is provided between the processing module 11 and the link cable 2 for converting information transmitted by the link cable 2 into information acceptable by the processing module 11 as well as converting information in the processing module 11 into information transmittable by the link cable 2. A memory 13 is provided in the processing module 11, as well as an I/O module 14 for controlling a unit to be controlled (not illustrated) that is connected to the slave station 3A.
FIG. 9 shows a conventional program in ladder form for executing an RFRP instruction. The RFRP instruction causes data to be received by the master station via the link cable from a slave station. A corresponding instruction is RTOP, which causes data to be transmitted by the master to a slave station. The RFRP instruction in FIG. 9 is an example of a conventional program for transferring data between the master station 1 and slave station 3A. In the ladder notation, the state symbol .parallel. indicates a "contact A" state condition and the state symbol .parallel. indicates a "contact B" state condition for the execution of an identified function.
Referring to FIG. 9, in a first program step S901 the state symbol 901 shows an active state condition for the START flag 6e that is provided in the internal device memory 6. The flag is set in the active state in order to initiate execution of the RFRP instruction in accordance with a program in the processing module 11. The inactive state condition of the PROCESSING EXECUTING flag 6b, and the inactive state condition of the PROCESSING COMPLETE flag 6c are shown by symbols 902 and 903, respectively. Thus, when the START flag 6e is reset, the PROCESSING EXECUTING flag 6b is in the set state, and the PROCESSING COMPLETE flag 6c is in the reset state, all of the conditions precedent to the execution of step S901 are satisfied. As a result, a 6D SET instruction 904 for setting a START CONDITION can be executed. This START CONDITION ESTABLISHING flag 6d is stored at an address indicated by 6D (904a) in the internal device memory 6.
Proceeding to step S902, the state symbol 905 indicates the active state of the START CONDITION ESTABLISHING flag 6d. When the START CONDITION ESTABLISHING flag 6d is set as a result of step S901, the condition precedent to execution of step S902 is satisfied and RFRP instruction 906 is executed. Since the PROCESSING EXECUTING flag 6b and the PROCESSING COMPLETE flag 6c are stored at addresses which depend on the hardware configuration, it is necessary to check the hardware configuration and specify calculated addresses in the sequence program when performing a read or write. The RFRP instruction 906 has operands n1 (906a), n2 (906b), n3 (906d) and D (906c). The instruction is used to transfer data from a particular slave station 3 to the master station 1 via the link cable 2. The instruction identifies the number of words, n3 (906d), starting at address n2 (906b) in the memory 13 of the processing module 11 of a slave station identified by n1 (906a), which are to be transferred to positions starting at address D (906c) of the link register 6a provided in the internal device memory 6 of the central data processing module 4 in the master station 1. When the transfer from slave to master according to this instruction has been completed, the PROCESSING COMPLETE flag 6c is set. As a result, the input conditions of steps S903 and S904 are satisfied, and a 6d reset instruction 907 and a 6b reset instruction 908 are executed. Address 6D (907a) identifies the location at which the START CONDITION ESTABLISHING flag 6d is stored, and address 6B (908a) identifies the location at which the PROCESSING EXECUTING flag 6b is stored.
The operation of the ladder language program shown in FIG. 9 may be described with reference to a timing chart illustrated in FIGS. 10A and 10B. When the RFRP instruction 906 is executed at step S902, the PROCESSING EXECUTING flag 6b is set at a point (1001) shown in FIG. 10A. This prevents execution of step S901 again until flag 6b is reset. When data transfer from the processing module 11 to the master station 1 is complete, the PROCESSING COMPLETE flag 6c is set at a point 1002 shown in FIG. 10B. When the PROCESSING COMPLETE flag 6c is set at step S903 in FIG. 9, the 6D RESET instruction 907 is executed, the START CONDITION ESTABLISHING flag 6d is reset, the 6B RESET instruction 908 is executed at step S904, and the PROCESSING EXECUTING flag 6b is reset at point 1003 shown in FIG. 10A. The PROCESSING COMPLETE flag 6c is automatically reset at a point 1004 after the PROCESSING EXECUTING flag 6b is reset, as shown in FIG. 10B.
As is clear from the above explanation, flags 6b and 6c act as interlock conditions that assure that there is no overlap in the execution of program instructions. Thus, until flags 6b and 6c are both reset, the initial conditions of instruction S901 cannot be met, preventing further execution of that instruction until the current instruction has been completed. If instructions subsequent to those shown in S901-S904 are provided with initial conditions like those in S901, an effective step-by-step interlock can be achieved.
However, the aforementioned process has disadvantages in that it is required to check whether or not the operation of the processing module 11 is complete in the sequence program itself. Interlock processing has to be performed in the sequence program itself rather than by the operating system (OS). Because they serve interlock functions, it is necessary to check the PROCESSING EXECUTING flag 6b and the PROCESSING COMPLETE flag 6c, the addresses of which depend on several factors including the hardware configuration and the processing module loading position, and to specify these addresses in the sequence program. When data transfer is made between the master and slave stations, using the RTOP or RFRP instructions, it is necessary to write an interlock into the processing program, as shown in FIG. 9, in order not to execute an instruction for data transfer with the slave station when one data transfer is already taking place.